This invention relates to an intercommunication network for use in carrying out communication among a plurality of processors, such as execution processor units, input/output processors, and the like, which are connected to one another through a system bus to form a multiprocessor system.
In a conventional intercommunication network of the type described, a plurality of processors are classifiable into an upper rank one composed of execution processing units and a lower rank one composed of input/output processors and the like. Therefore, the execution processing units and the input/output processors will be hereinunder called upper and lower rank processors, respectively, when they are distinguished from each other.
In general, when a transmission or communication request takes place at a first one of the processors used as a transmission end or source to start communication with a second one of the processors that is operable as a reception or destination end, the first processor supplies the bus with a processor number preassigned to the second processor in addition to an intercommunication command. In this connection, such a processor number may be referred to as a destination processor number. Each of the processors always monitors the destination processor number on the bus to detect whether or not the destination processor number is destined to each processor. To this end, the destination processor number is compared with a preassigned processor number assigned to each processor. In the above-mentioned example, the second processor alone receives and detects the destination processor number to judge that the destination processor number is destined to the second processor. Thereafter, the second processor supplies an interruption request to a control circuit operable in accordance with firmware. As a result, the second processor is put into a communicable state with the first processor.
An intercommunication network of the above-mentioned type is very effective to carry out intercommunication between processors, such as execution processor units, both of which belong to the same rank and which do not have a master-slave relationship.
On the other hand, it often happens that similar intercommunication is carried out between an upper rank processor and a lower rank processor. In this event, a transmission end transmits a destination processor number to a reception end like in the intercommunication between the execution processor units.
More specifically, when the upper rank processor and the lower rank processor act as the transmission and the reception ends, respectively, so as to transfer a communication signal from the upper rank processor to the lower rank one, the upper rank processor supplies the lower rank processor with a destination processor number assigned to the lower rank processor. Thus, each upper rank processor is communicable with all the lower rank processors by specifying the lower rank processors by the destination processor number.
To the contrary, when a communication request takes place at a lower rank processor which is operable as the transmission end, so as to transfer a data signal sequence to be processed by the upper rank processors, the lower rank processor produces a destination processor number assigned to a selected one of the upper rank processors to indicate the selected upper rank processor. However, it is to be noted that the data signal sequence produced from the lower rank processor may be often processed in any one of the upper rank processors, if each of the upper rank processors can carry out processing in similar manners. In this event, it is not always desirable to specify a selected one of the upper rank processors by producing the destination processor number preassigned to the selected upper rank processor and to monitor a state of the selected upper rank processor in the lower rank processor. Specifically, each lower rank processor should always be conscious of a destination processor number communicable with each lower rank processor and must transmit such a destination processor number on transmission of the transmission request. Therefore, each lower rank processor must be formed by the use of complexed hardware and firmware and should bear comparatively heavy load.